Uniform Memory Access (UMA)

Figure 4.3: Bus-based UMA (SMP) shared memory system.

• In the UMA system a shared memory is accessible by all processors through an interconnection network in the same way a single processor accesses its memory.
• All processors have equal access time to any memory location. The interconnection network used in the UMA can be a single bus, multiple buses, or a crossbar switch.
• Because access to shared memory is balanced, these systems are also called SMP (symmetric multiprocessor) systems. Each processor has equal opportunity to read/write to memory, including equal access speed.
  • A typical bus-structured SMP computer, as shown in Fig. 4.3, attempts to reduce contention for the bus by fetching instructions and data directly from each individual cache, as much as possible.
  • In the extreme, the bus contention might be reduced to zero after the cache memories are loaded from the global memory, because it is possible for all instructions and data to be completely contained within the cache.
• This memory organization is the most popular among shared memory systems. Examples of this architecture are Sun Starfire servers, HP V series, and Compaq AlphaServer GS, Silicon Graphics Inc. multiprocessor servers.