Shared Memory System Coherence

• The four combinations to maintain coherence among all caches and global memory are:
  1. Write-update and write-through;
  2. Write-update and write-back;
  3. Write-invalidate and write-through;
  4. Write-invalidate and write-back.
• If we permit a write-update and write-through directly on global memory location X, the bus would start to get busy and ultimately all processors would be idle while waiting for writes to complete.
• In write-update and write-back, only copies in all caches are updated. On the contrary, if the write is limited to the copy of X in cache Q, the caches become inconsistent on X. Setting the dirty bit prevents the spread of inconsistent values of X, but at some point, the inconsistent copies must be updated.