Cache-Cache Coherence

Figure 4.7: Write-Update vs. Write-Invalidate.

• In multiprocessing system, when a task running on processor P requests the data in global memory location X, for example, the contents of X are copied to processor P's local cache, where it is passed on to P.
• Now, suppose processor Q also accesses X. What happens if Q wants to write a new value over the old value of X?
• There are two fundamental cache coherence policies:
  1. write-invalidate,
  2. write-update (see Fig. 4.7).
• Write-invalidate maintains consistency by reading from local caches until a write occurs. When any processor updates the value of X through a write, posting a dirty bit for X invalidates all other copies.
  • For example, processor Q invalidates all other copies of X when it writes a new value into its cache. This sets the dirty bit for X.
  • Q can continue to change X without further notifications to other caches because Q has the only valid copy of X.
  • However, when processor P wants to read X, it must wait until X is updated and the dirty bit is cleared.
• Write-update maintains consistency by immediately updating all copies in all caches.
  • All dirty bits are set during each write operation. After all copies have been updated, all dirty bits are cleared.