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Shared Memory System Coherence
- The four combinations to maintain coherence among all caches and global memory are:
- Write-update and write-through;
- Write-update and write-back;
- Write-invalidate and write-through;
- Write-invalidate and write-back.
- If we permit a write-update and write-through directly on global memory location X, the bus would start to get busy and ultimately all processors would be idle while waiting for writes to complete.
- In write-update and write-back, only copies in all caches are updated. On the contrary, if the write is limited to the copy of X in
cache Q, the caches become inconsistent on X. Setting the dirty bit prevents the spread of inconsistent values of X, but at some point, the inconsistent copies must be updated.
Cem Ozdogan
2006-12-27